Regviz

Microchip Technology /ATSAMV70Q20B /USART0 /US_IER_SPI_MODE

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as US_IER_SPI_MODE

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/Microchip Technology/ATSAME70N20B/USART0/US_IER_SPI_MODE#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (RXRDY)RXRDY 0 (TXRDY)TXRDY 0 (OVRE)OVRE 0 (TXEMPTY)TXEMPTY 0 (UNRE)UNRE 0 (NSSE)NSSE

Description

Interrupt Enable Register

Fields

RXRDY

RXRDY Interrupt Enable
TXRDY

TXRDY Interrupt Enable
OVRE

Overrun Error Interrupt Enable
TXEMPTY

TXEMPTY Interrupt Enable
UNRE

Underrun Error Interrupt Enable
NSSE

NSS Line (Driving CTS Pin) Rising or Falling Edge Event

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data